The RTL also includes a bus slave and a decode logic specific to the bus protocol (AHB, APB, AXI, AXI-Lite, or proprietary), ensuring instant connection of the application logic to the register bus. The generated RTL Code (VHDL, Verilog, SystemVerilog or SystemC) for the registers is human-readable with easy-to-follow comments. Users are able to convert register spec from IP-XACT to UVM or from SystemRDL to IP-XACT.īased on the golden specification, various SoC teams can use the high-performance code generators via GUI or command line. This methodology enables you to work on different parts of the design in parallel with a large team. Built with high-performance IP-XACT compiler and SystemRDL compiler, simple and complex registers can be created hierarchically such that large SoC designs are divided into manageable sub-blocks that are represented symbolically, designed and connected together. Equipped with user-friendly templates, you can specify your registers using any of the add-ins to Word, Excel, OpenOffice Calc or FrameMaker.
